1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device. Specifically, the present invention relates to a method for manufacturing a semiconductor device having an interconnect structure, in which a refractory metal layer containing titanium (Ti) or tantalum (Ta) is provided on a metal interconnect when an interconnect layer for mutually coupling elements is formed on an upper portion of the substrate having a semiconductor device formed therein.
2. Related Art
In recent years, in response to increasing of integrations and operating speeds of semiconductor devices, reductions in interconnect resistances and in interconnect capacitances are required. Further, in semiconductor devices having multiple-layered interconnect structures, aluminum, copper or the like is employed for an interconnect material, and in such configuration, a barrier metal layer is generally provided for preventing metal elements from diffusing into an insulating film.
Japanese Laid-Open Publication No. 2004-235,344 discloses a technique for removing fluorocarbon by performing a treatment with an organic chemical solution between a plasma etching process and an ashing process, so as to inhibit an emission of active species of fluorine or fluorocarbon emitted from a resist in the ashing process.
Japanese Laid-Open Publication No. H10-154,694 discloses a method for manufacturing a semiconductor integrated circuit device including a resist-reproduction process, in which a first photo resist for employing a patterning of an aluminum thin film containing at least one of silicon and copper is removed, and then a second photo resist is applied on such aluminum thin film.
Meanwhile, when larger number of half-finished products are present in the practical manufacturing process, a stand-by time between operations may often be increased. In the manufacturing process described in Japanese Laid-Open Publication No. 2004-235,344, some products in some production lots are in a condition of being left for longer duration of time since a treatment with an organic chemical solution after a plasma etching step is finished until the next ashing step is started. In this case, exposed portions of a metal nitride film disposed in the bottom of the via is oxidized by being exposed for a long time with water in an atmospheric air.
In case that the exposed portions of the metal nitride film of the via bottom are oxidized, a resistance of via (via resistance) as being applied by a voltage may possibly increase at the time of filling a via hole with, for example, tungsten to form the via. As a result, a reliability of the obtained semiconductor device may often be reduced.
Conventionally, a certain limitation in time for starting from the treatment with organic chemical solution until ending the ashing step and a certain process control between steps are required for preventing an oxidization in the exposed portion of a metal nitride film of the via bottom, leading to a decrease in the productivity.
On the other hand, it is also considered that an oxide film on a surface of the metal nitride film in the via bottom may be restored to the original state by a reduction process. Nevertheless, the oxide film on the surface of the metal nitride film in the via bottom is in a so-called “rusted” condition, and the level of unevenness in the surface is influenced by: (1) a quantity of water contained in atmospheric air in a manufacturing line; (2) a quantity of electric charge accumulated in an interconnect; (3) quantities of titanium fluorides (hereinafter generally referred to as “TiF”) and titanium oxyfluorides (hereinafter generally referred to as “TiOF”) in the exposed portions, or the like, and forms of the unevenness are various, and larger level of unevenness may often provide a complete cavity formed therein. It is difficult that oxidized titanium is restored to the original state of titanium (Ti) including a geometry of a titanium layer before being oxidized. More specifically, it is required to prevent an oxidization of the via bottom for providing an improved reliability of the semiconductor device.
The present invention is established on the basis of such technical problems, and an object of the invention is to provide a technique, which is capable of eliminating needs for a certain limitation in time for starting from the treatment with organic chemical solution until ending the ashing step after etching step for forming the via hole and a certain process control between steps, and of preventing an oxidization of a metallic nitride film of the via bottom.